1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of a semiconductor device.
2. Description of the Related Art
Currently, in manufacturing high-performance semiconductor transistors, so-called SOI (Silicon-On-Insulator) substrates (substrates each having a buried insulation film such as a silicon oxide film interposed between a silicon supporting substrate and a surface silicon layer) are beginning to be in use, instead of monocrystalline silicon substrates, in order to realize improvement in the operation speed and reduction in power consumption of the semiconductor transistors.
The semiconductor transistors using the SOI substrates are roughly classified into fully-depleted (FD) SOI transistors, partially-depleted SOI transistors, and so on. The fully-depleted SOI transistor among these transistors has advantages of enabling reduction in power consumption by a low parasitic capacitance, enabling the use of a so-called metal gate (the change of a material of a gate electrode from polycrystalline silicon to metal) by a low threshold voltage, and so on.
In this fully-depleted SOI transistor, a region surrounded by a source region, a drain region, and a buried insulation film is substantially fully depleted while in operation. This naturally necessitates making the thickness of a silicon active layer of the SOI substrate smaller than that in the case of the partially-depleted SOI transistor.
As the fully-depleted SOI transistor, those having a double gate structure in which a channel region is sandwiched by two gate electrode layers have been developed. The use of the double gate structure makes it possible to enhance controllability in forming the gate electrode layers and to further promote structure miniaturization. This also makes it possible to lower impurity concentration in the channel region to thereby alleviate impurity scattering and an electric field in a depth direction of the channel region. Consequently, in the transistor, it is possible to enhance carrier mobility in the channel region to increase a drive current. Further, since the transistor is operated while the channel region is in a completely depleted state, it is possible to lower a so-called S-factor to an ideal value of about 60 mV/decade to lower a threshold voltage value of the transistor.